The use of plasma in semiconductor device fabrication provides directionality, low temperature, and processing convenience. Accordingly, plasma is typically used in etch and deposition processes for fabricating semiconductor devices. However, the plasma also introduces a potential for increased semiconductor damage due to surface charging of a semiconductor device. This surface charging during the plasma processing is often referred to as plasma charging damage. As the thickness of a gate oxide layer continue to decrease to improve device performance, the plasma charging damage is becoming a large concern because it can severely and directly degrade the electrical properties of the gate oxide layer. Especially, after the formation of a first metallic interconnect having the highest antenna ratio among metallic interconnects and in contact with a transistor, the probability of the occurrence of the plasma charging damage is getting greater. However, a conventional Pre-Metallic Dielectric (PMD) layer does not contain any material that can prevent the occurrence of the plasma charging damage.
Referring to FIG. 1, a conventional PMD layer including a nitride layer 11 as an etching stop layer, a BPSG layer 12, and an oxide layer 13 as a capping layer are placed on a substrate with at least one structure. A metallic interconnect 14 is placed on the PMD layer. A first Inter-Layer Dielectric (ILD) 15, a second insulating layer 16, a second metallic interconnect 17, and a second ILD 18 are sequentially and repeatedly placed on the device.
However, the nitride layer 11, the BPSG 12, and the oxide layer 13 have shortcomings such as poor charge preservation and are, therefore, unable to protect the semiconductor device from the plasma charging damage.